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Author
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Topic:ðð How exactly are chips produced on those giant cookie sheets anyway?
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jeremyh
Junior Member
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posted 02-14-2001 02:18 PM ððð
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Different
speed grades also occur on the same wafer because the diffusion process
is not an exact one. You will receive a gradiation across the wafer.
Imagine spraying a can of spray paint. It's real dark in the middle and
lighter as you travel outward. This is an exaggeration of course, but
the wafer variation effect is somewhat similar. Now, what if you spray
slightly at an angle, the pattern changes, right? Well, similar things
happen during fabrication. There is no such thing as infinite precision
when it comes to mechanical alignments and certainly when it comes to
the science/art of wafer fabrication. The result is that if you've
designed, say, a 100 Ohm resistor into your design and the process hits
the nail on the head, perfectly centered typical silicon, you will get
100 Ohms (or very close to it) on the majority of the die in the middle
of the wafer. However as you move towards the edges you will see
gradiation - 99.5 Ohms, 99 Ohms, or maybe 100.5, 101 Ohms. Now, some
circuits use a current source wherein the resistor value controls the
current, or power that is consumed by the circuit. Generally, the more
power used, the faster the circuit. So as these variations occur you
will get some circuits that perform faster than others upon the same
wafer. Similar effects can be seen in the creation of the transistors
as some will end up being faster than others due to different doping
levels, or metal etch that can change the parasitics, etc. Combine all
these variations together and you can get a certain amount of variation
across the wafer. Consider that the manufacturer want to be
conservative in qualifying parts so that they don't get returns, and it
becomes harder and harder to get the fastest material. This also
explains why you can always overclock CPUs to some extent, and some
more than others.Hopefully that explains how you can get different speed grades on the same wafer. -Jeremy (comm IC designer and dieing to get his new 733 MHz Mac) IP: Logged |
Bodhi
Member
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posted 02-14-2001 02:33 PM ððð
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So the
whole process is finished and at that point is when you hook the
processors up and find out that maybe out of a sheet of silicon, you
got only 30% of the processors to run at the speed you intended, right?------------------
~~Bodhi~~
~~Peace~~
Homer (reading Internet for Dummies): Wow... they've got the Internet on computers now? IP: Logged |
Motoman
Member
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posted 02-14-2001 04:18 PM ððð
ðð ðð ðð ðð
Eskimo÷
great thread man. Same to everyone else who has contributed. IÌve
always worked in the functional domain and have very little experience
with how the process works. Your post hand down beat every book IÌve
ever read on the topic. DidnÌt realize this was such an old topicWhile
everything Eskimo has said is true hereÌs how it trickles up to the
design world. Based on a functional standpoint the maximum frequency of
any IC is a function of its timing parameters. The timing parameters
are defined by all the great info talked about earlier. LetÌs
say you have two flip-flops ( MOSFET switches ) in series (output of
one is driving the input of the second). The maximum clock speed of
this circuit is defined as Fmax = 1 / ( Th1 + Tpg1 + Trf1 + Th2 + Tpg2 + Trf2) Where Th = is the setup time in ns
Tpg = signal propagation delay in ns
Trf = larger of rise or fall time in ns
Subscript 1 = flop 1 (2 = flop 2) You
can see as the parameters are smaller fmax goes up. All of these values
can be found on the product white paper. Anyway by shrinking the
process the parameters will go from 4ns to 2ns for example. So if on one process with the parameters set at 4ns the fmax is 41Mhz
Now on the smaller process (2ns) the fmax is now 83Mhz. All
this is done without having to change any of the functional design.
ItÌs a free speed boost by just changing from one process to the next.
Adding more flops in series causes the fmax to go down. This is one of
the reasons why everyone is removing flops and stretching the pipe
(less flops per stage but more stages). Anyway just gives you a little different perspective on how the same things work but looking at it from the design approach.
IP: Logged |
MacAgent
Member
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posted 02-14-2001 04:46 PM ððð
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Wow, this whole thread actually made sense!  Now there are just a few more things I don't understand, I'll post the biggest one: How the heck do 1s and 0s turn into a picture on the screen?!  ------------------
Get your Apple stuff here! d IP: Logged |
jeremyh
Junior Member
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posted 02-14-2001 05:59 PM ððð
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Bodhi,That's
correct. The parts can be binned out seperately based on their speed
grade. I can't vouch exactly for CPUs since I deal with a different
kind of IC, but generally you would look for a certain amount of
functionality at wafer sort, send them off the packaging, and then at
final sort you would bin them out into different speed classes. The stuff I work with is spec'd out at one speed only so it's either good or it's crap. 
If we have to take a yield hit we try to identify the crap before
packaging the parts because it costs money to package them. It isn't
possible to test the parts I work on at operating frequency at wafer
sort (the parts I work on run at frequencies of 2.5-10 GHz), and may
not be for CPUs either since the standard wafer sort frequency is only
around 5 MHz, due to the parasitics of the tester and the tester
probes. Sometimes you can determine if parts are going to pass or fail
based on parametrics, which are DC tests that give you an idea of how
the device is going to perform when it's run at speed. This can help
you screen out some of the garbage before it goes to assembly. Some
other forum I read that the new 733s are starting to yield "fairly
well" at 7% or something, which shocked me if it's true because that's
really low compared to what I'm used to (70% is more along the lines of
what I'm used to). However the stuff I work on, although being very
high speed, tends to also be very small which means the odds of having
a defect on a given die (chip) are much lower resulting in high working
pieces. Edited to fix a spelling error (not that that's the only one..) [This message has been edited by jeremyh (edited 02-15-2001).] IP: Logged |
Bodhi
Member
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posted 02-14-2001 06:45 PM ððð
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That was Motoman. He said the 7450 G4's were getting an 8% yeild.Eskimo / Motoman - Is this considered an average yeild for a chip like a G4 or AMD? With
all of the money that is spent by Motorola for the machines that make
these chips and the amount that do not ever come out like you want them
which end up being recycled, and the 7450 is probably sold to Apple for
$200 a chip, how do you make money off of this process? ------------------
~~Bodhi~~
~~Peace~~
Homer (reading Internet for Dummies): Wow... they've got the Internet on computers now? IP: Logged |
Eskimo
Moderator
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posted 02-14-2001 08:47 PM ððð
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No
Bodhi, 8% is a dismal number and you are correct I doubt at those
numbers Moto is really making much money off of them. But they will
improve their numbers soon (hopefully) in order to supply their order
from Apple. On a well established process that has matured you can see
yields in the 80% range. On new processes 50% or better is pretty darn
good. The 7450 is a brand new chip on a relatively new process for
Moto, it isn't that surprising that they are taking early yield hits.jeremyh
is absolutely correct that at sort we are unable to test the exact
speeds. We do however as he indicated perform several parametric tests
which can indicate speeds. Basically it is an array of many logical
inverters tied end to end in a ring. The frequency at which we can get
to to switch it can indicate final die speeds. Motoman's post explains
how the timing delays in this structure would allow you to do that. We
only package good die of course that are known to operate. I'm pretty
sure I discussed sort in Chapter 7 or so. After packaging we can do the
actual speed binning and burn in. IP: Logged |
EDGar
Junior Member
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posted 02-16-2001 09:08 PM ððð
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One of the best threads I have seen in a long time!Eskimo, just a question of scale, are all the photos of wafers the same 200mm diameter mentioned in the beginning? It
also looked like some of the die simply ran off the end of the wafer,
producing sortof half die, which obviously won't work. Is this easier
than designing the process to only work on the wafer? hmm,
what happens to all of the wafers that don't pass? Can the materials be
resused or are they so cheap that they are simply scrapped?
Mr. Poe
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"The abstract poet prominent like Shakespeare" ONON IP: Logged |
Eskimo
Moderator
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posted 02-16-2001 09:43 PM ððð
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Yes, all the photo's I provided are of 200mm wafers. There are other sizes used in industry such as 150mm (6") and 100mm (4").Yes
it is true that some die are printed only partially on the wafer, this
is due to the stepping/scanning motion that happens at the
photolithography step. I think I talked about this in one of my
chapters. You try to minimize your edge die that will be cut off but
you can't help it, they just don't fit on perfectly. And it's easier to
just print accross the whole surface. These
wafers are fairly cheap in relation to their final worth if they work.
But they still cost maybe around 100-200 dollars. So often you try to
recycle them. There are companies dedicated to buying scrapped wafers,
stripping all the layers off of them, and melting them down to make new
wafers. IP: Logged | |
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